Nonvolatile memory retains stored data when power is removed and is desirable in many different applications. As system-on-chips (SoCs) become more prevalent in consumer electronics and industrial applications, embedded nonvolatile memories have become more common. Embedded memory is incorporated onto the same underlying semiconductor die and non-memory circuitry.
The embedded memory is used for various purposes, among which are chip IDs, analog trimming, yield enhancement, and code storage. It would be advantageous if the embedded memories did not require added masks and process modifications to a standard CMOS flow. “Flash” memory that uses multiple polysilicon layers is not compatible with standard CMOS flow. As a result, gate dielectric based anti-fuse memory increasingly has become the choice of SoC chip designers because it is standard CMOS process based, reliable, and secure.
Gate dielectric anti-fused based memory can be broadly categorized into two groups, depending upon its operating principle. The first type is a cross-point memory consisting of a single capacitor at each gridpoint. The second type has more than two access lines for each cell in the memory array. A typical example is a storage capacitor or transistor coupled in series with a selection device such as a transistor or diode. Examples of the first type can be found in U.S. Pat. Nos. 6,898,116, 6,992,925, 7,638,855, and 7,110,278. An example of the second type is U.S. Pat. No. 6,667,902 (and the references cited therein).
Cross-point memory arrays are advantageous due to its compact layout and simple decoding. As a result, embedded OTP memories of this type can be about eight times smaller than those of the second type. However, prior art cross-point OTP memories have drawbacks, such as significant process complexity, array leakage current, and reliability.
Furthermore, for embedded applications, it is very important to comply with logic layout design rules while introducing no extra process steps or only non-critical ones. As shown in prior art FIG. 1 (FIG. 2 of U.S. Pat. No. 7,638,855 to Lung), disclosed is a cross-point antifuse memory that requires significant changes in standard CMOS process flow and needs additional critical implant masks because the N+ bit lines and P-isolations are not self-aligned. In addition, the gate dielectric before programming and the P+/N+ diode formed after programming can have questionable quality.
U.S. Pat. Nos. 6,898,116 and 6,992,925, as illustrated in prior art FIG. 2 (FIG. 28 from the '925 patent), attempted to solve these problems using standard MOSFETs by adding buried N+ or P+ bodies. In the '925 patent, there are source and drain regions that extend under the sidewall spacers, thereby connecting to the channel region under the gates. Due to the presence of source and drain regions, however, there are two potential disadvantages with this cell. First, program disturb from inhibit voltages applied to the body can occur for un-selected cells where the gate is biased at zero voltage and body at Vpp. Due to impact ionization and other high voltage mechanisms, the floating source/drain can be charged up to a voltage well above ground. As a result, the MOSFET device can be fully inverted and a large percentage of the inhibit voltage drops across the gate dielectric. Secondly, the gate dielectric may breakdown at the overlap region between the gate and LDD. When this happens at two neighboring cells, there will be a path for leakage current during both programming and read operations.
U.S. Pat. No. 7,110,278 to Keshavarzi discloses a cross-point memory similar to that of Peng except that the source and drain of each MOSFET is disconnected from its neighbors, as shown in prior art FIG. 3 (FIG. 2 of the '278 patent). The cell is bigger as a result of the non-continuous active regions. Furthermore, program disturb from the body can remain a problem because source and drain doped regions are still present for each MOSFET transistor.
Consequently, there is a need for a cross-point anti-fuse OTP memory that offers not only a compact size but also logic CMOS compatibility, low leakage current, and improved program reliability.